1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device having a surrounding gate transistor (SGT) which is a three-dimensional semiconductor.
2. Description of the Related Art
Based on miniaturization, a planar transistor is used in a wide range of fields, such as computers, communication devices, measurement devices, automatic control devices and domestic devices, as a low-power consumption, low-cost, high-throughput microprocessor, ASIC or microcomputer, and a low-cost, large-capacity memory. However, the planar transistor is two-dimensionally formed on a semiconductor substrate. Specifically, in the planar transistor, a source, a gate and a drain are horizontally structured on a surface of a silicon substrate. In contrast, an SGT is formed in a structure where a source, a gate and a drain are arranged in a vertical direction with respect to a silicon substrate, wherein the gate is formed to surround a convex semiconductor layer (see, for example, the following Non-Patent Document 1, FIG. 144). Thus, in the SGT, an occupancy area can be largely reduced as compared with the planar transistor.
However, in the SGT, a gate length becomes shorter along with miniaturization of ultra-large-scale integrated (ULSI) circuits, so that an off-leak current, i.e., a drain current when a voltage is applied to a drain electrode under a condition that a voltage applied to each of a gate electrode and a source electrode is zero V, becomes larger.
As means to reduce such an off-leak current, there has been known a technique of forming a source and a drain in a cup-like or concave structure, as disclosed, for example, in the following Non-Patent Document 2 and Patent Document 1.
An SGT structure having a conventional source/drain structure as disclosed in the Non-Patent Document 2 is shown in FIGS. 139 and 140. As is clear, particularly, from FIG. 140, the conventional source/drain structure has a horizontally flat distribution. Differently, in a source formed in a concave structure as shown in FIGS. 141 and 142, a potential barrier between the source and a pillar body during application of a voltage to a drain can be increased as compared with the conventional structure, to provide a higher punch-through voltage. Particularly, a much higher punch-through voltage can be provided by reducing a length X which is a depth of a source or drain.
Further, as disclosed in the Patent Document 1, it is also studied to form each of a source and a drain in a concave structure (FIG. 143).